[llvm] 972212d - [ConstraintElimination] Add tests for signed predicates.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 1 05:23:27 PST 2021
Author: Florian Hahn
Date: 2021-02-01T13:23:05Z
New Revision: 972212d29c3ad0569afb9dbed38a6cab7311db3e
URL: https://github.com/llvm/llvm-project/commit/972212d29c3ad0569afb9dbed38a6cab7311db3e
DIFF: https://github.com/llvm/llvm-project/commit/972212d29c3ad0569afb9dbed38a6cab7311db3e.diff
LOG: [ConstraintElimination] Add tests for signed predicates.
Add test coverage for conditions with signed predicates.
Added:
llvm/test/Transforms/ConstraintElimination/mixed-signed-unsigned-predicates.ll
llvm/test/Transforms/ConstraintElimination/sge.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/ConstraintElimination/mixed-signed-unsigned-predicates.ll b/llvm/test/Transforms/ConstraintElimination/mixed-signed-unsigned-predicates.ll
new file mode 100644
index 000000000000..0cb076f4b4b3
--- /dev/null
+++ b/llvm/test/Transforms/ConstraintElimination/mixed-signed-unsigned-predicates.ll
@@ -0,0 +1,221 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -constraint-elimination -S %s | FileCheck %s
+
+define i1 @test_add_nuw(i8 %start, i8 %low, i8 %high) {
+; CHECK-LABEL: @test_add_nuw(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ADD_PTR_I:%.*]] = add nuw i8 [[START:%.*]], 3
+; CHECK-NEXT: [[C_1:%.*]] = icmp uge i8 [[ADD_PTR_I]], [[HIGH:%.*]]
+; CHECK-NEXT: br i1 [[C_1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[UC_3:%.*]] = icmp ugt i8 [[START]], [[HIGH]]
+; CHECK-NEXT: [[START_1_1:%.*]] = add nuw i8 [[START]], 1
+; CHECK-NEXT: [[UC_4:%.*]] = icmp uge i8 [[START_1_1]], [[HIGH]]
+; CHECK-NEXT: [[RES_11:%.*]] = xor i1 [[UC_3]], [[UC_4]]
+; CHECK-NEXT: [[START_3_1:%.*]] = add nuw i8 [[START]], 3
+; CHECK-NEXT: [[T_0:%.*]] = icmp uge i8 [[START_3_1]], [[HIGH]]
+; CHECK-NEXT: [[RES_12:%.*]] = xor i1 [[RES_11]], true
+; CHECK-NEXT: [[UC_5:%.*]] = icmp ugt i8 [[START_3_1]], [[HIGH]]
+; CHECK-NEXT: [[RES_13:%.*]] = xor i1 [[RES_12]], [[UC_5]]
+; CHECK-NEXT: [[SC_8:%.*]] = icmp sge i8 [[START_1_1]], [[HIGH]]
+; CHECK-NEXT: [[RES_14:%.*]] = xor i1 [[RES_13]], [[SC_8]]
+; CHECK-NEXT: [[SC_9:%.*]] = icmp sge i8 [[START_3_1]], [[HIGH]]
+; CHECK-NEXT: [[RES_15:%.*]] = xor i1 [[RES_14]], [[SC_9]]
+; CHECK-NEXT: ret i1 [[RES_15]]
+; CHECK: if.else:
+; CHECK-NEXT: [[F_0:%.*]] = icmp ugt i8 [[START]], [[HIGH]]
+; CHECK-NEXT: [[START_1:%.*]] = add nuw i8 [[START]], 1
+; CHECK-NEXT: [[F_1:%.*]] = icmp uge i8 [[START_1]], [[HIGH]]
+; CHECK-NEXT: [[RES_0:%.*]] = xor i1 false, false
+; CHECK-NEXT: [[SC_1:%.*]] = icmp sgt i8 [[START]], [[HIGH]]
+; CHECK-NEXT: [[RES_1:%.*]] = xor i1 [[RES_0]], [[SC_1]]
+; CHECK-NEXT: [[SC_2:%.*]] = icmp sge i8 [[START_1]], [[HIGH]]
+; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[SC_2]]
+; CHECK-NEXT: [[START_2:%.*]] = add nuw i8 [[START]], 2
+; CHECK-NEXT: [[F_2:%.*]] = icmp uge i8 [[START_2]], [[HIGH]]
+; CHECK-NEXT: [[RES_3:%.*]] = xor i1 [[RES_2]], false
+; CHECK-NEXT: [[SC_3:%.*]] = icmp sge i8 [[START_2]], [[HIGH]]
+; CHECK-NEXT: [[RES_4:%.*]] = xor i1 [[RES_3]], [[SC_3]]
+; CHECK-NEXT: [[SC_4:%.*]] = icmp sle i8 [[START_2]], [[START_1]]
+; CHECK-NEXT: [[RES_5:%.*]] = xor i1 [[RES_4]], [[SC_4]]
+; CHECK-NEXT: [[START_3:%.*]] = add nuw i8 [[START]], 3
+; CHECK-NEXT: [[F_3:%.*]] = icmp uge i8 [[START_3]], [[HIGH]]
+; CHECK-NEXT: [[RES_6:%.*]] = xor i1 [[RES_5]], false
+; CHECK-NEXT: [[SC_5:%.*]] = icmp sge i8 [[START_3]], [[START_1]]
+; CHECK-NEXT: [[RES_7:%.*]] = xor i1 [[RES_6]], [[SC_5]]
+; CHECK-NEXT: [[START_4:%.*]] = add nuw i8 [[START]], 4
+; CHECK-NEXT: [[UC_2:%.*]] = icmp uge i8 [[START_4]], [[HIGH]]
+; CHECK-NEXT: [[RES_8:%.*]] = xor i1 [[RES_7]], [[UC_2]]
+; CHECK-NEXT: [[SC_6:%.*]] = icmp sge i8 [[START_4]], [[START_1]]
+; CHECK-NEXT: [[RES_9:%.*]] = xor i1 [[RES_8]], [[SC_6]]
+; CHECK-NEXT: [[SC_7:%.*]] = icmp sge i8 [[START_4]], [[HIGH]]
+; CHECK-NEXT: [[RES_10:%.*]] = xor i1 [[RES_9]], [[SC_7]]
+; CHECK-NEXT: ret i1 [[RES_10]]
+;
+entry:
+ %add.ptr.i = add nuw i8 %start, 3
+ %c.1 = icmp uge i8 %add.ptr.i, %high
+ br i1 %c.1, label %if.then, label %if.else
+
+
+if.then:
+ %uc.3 = icmp ugt i8 %start, %high
+ %start.1.1 = add nuw i8 %start, 1
+ %uc.4 = icmp uge i8 %start.1.1, %high
+ %res.11 = xor i1 %uc.3, %uc.4
+
+ %start.3.1 = add nuw i8 %start, 3
+ %t.0 = icmp uge i8 %start.3.1, %high
+ %res.12 = xor i1 %res.11, %t.0
+
+ %uc.5 = icmp ugt i8 %start.3.1, %high
+ %res.13 = xor i1 %res.12, %uc.5
+
+ %sc.8 = icmp sge i8 %start.1.1, %high
+ %res.14 = xor i1 %res.13, %sc.8
+
+ %sc.9 = icmp sge i8 %start.3.1, %high
+ %res.15 = xor i1 %res.14, %sc.9
+
+ ret i1 %res.15
+
+if.else:
+ %f.0 = icmp ugt i8 %start, %high
+ %start.1 = add nuw i8 %start, 1
+ %f.1 = icmp uge i8 %start.1, %high
+ %res.0 = xor i1 %f.0, %f.1
+
+ %sc.1 = icmp sgt i8 %start, %high
+ %res.1 = xor i1 %res.0, %sc.1
+
+ %sc.2 = icmp sge i8 %start.1, %high
+ %res.2 = xor i1 %res.1, %sc.2
+
+ %start.2 = add nuw i8 %start, 2
+ %f.2 = icmp uge i8 %start.2, %high
+ %res.3 = xor i1 %res.2, %f.2
+
+ %sc.3 = icmp sge i8 %start.2, %high
+ %res.4 = xor i1 %res.3, %sc.3
+
+ %sc.4 = icmp sle i8 %start.2, %start.1
+ %res.5 = xor i1 %res.4, %sc.4
+
+ %start.3 = add nuw i8 %start, 3
+ %f.3 = icmp uge i8 %start.3, %high
+ %res.6 = xor i1 %res.5, %f.3
+
+ %sc.5 = icmp sge i8 %start.3, %start.1
+ %res.7 = xor i1 %res.6, %sc.5
+
+ %start.4 = add nuw i8 %start, 4
+ %uc.2 = icmp uge i8 %start.4, %high
+ %res.8 = xor i1 %res.7, %uc.2
+
+ %sc.6 = icmp sge i8 %start.4, %start.1
+ %res.9 = xor i1 %res.8, %sc.6
+
+ %sc.7 = icmp sge i8 %start.4, %high
+ %res.10 = xor i1 %res.9, %sc.7
+
+ ret i1 %res.10
+}
+
+define i1 @test_and_ule_sge(i32 %x, i32 %y, i32 %z, i32 %a) {
+; CHECK-LABEL: @test_and_ule_sge(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C_1:%.*]] = icmp ule i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[C_2:%.*]] = icmp sle i32 [[Y]], [[Z:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = and i1 [[C_1]], [[C_2]]
+; CHECK-NEXT: br i1 [[AND]], label [[THEN:%.*]], label [[ELSE:%.*]]
+; CHECK: then:
+; CHECK-NEXT: [[UC_1:%.*]] = icmp ule i32 [[X]], [[Z]]
+; CHECK-NEXT: [[UC_2:%.*]] = icmp ule i32 [[X]], [[Y]]
+; CHECK-NEXT: [[RES_1:%.*]] = xor i1 [[UC_1]], true
+; CHECK-NEXT: [[UC_3:%.*]] = icmp ule i32 [[Y]], [[Z]]
+; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[UC_3]]
+; CHECK-NEXT: [[UC_4:%.*]] = icmp ule i32 [[X]], [[A:%.*]]
+; CHECK-NEXT: [[RES_4:%.*]] = xor i1 [[RES_2]], [[UC_4]]
+; CHECK-NEXT: [[SC_1:%.*]] = icmp sle i32 [[X]], [[Z]]
+; CHECK-NEXT: [[RES_5:%.*]] = xor i1 [[RES_4]], [[SC_1]]
+; CHECK-NEXT: [[SC_2:%.*]] = icmp sle i32 [[X]], [[Y]]
+; CHECK-NEXT: [[RES_6:%.*]] = xor i1 [[RES_5]], [[SC_2]]
+; CHECK-NEXT: [[SC_3:%.*]] = icmp sle i32 [[Y]], [[Z]]
+; CHECK-NEXT: [[RES_7:%.*]] = xor i1 [[RES_6]], [[SC_3]]
+; CHECK-NEXT: [[SC_4:%.*]] = icmp sle i32 [[X]], [[A]]
+; CHECK-NEXT: [[RES_8:%.*]] = xor i1 [[RES_7]], [[SC_4]]
+; CHECK-NEXT: ret i1 [[RES_8]]
+; CHECK: else:
+; CHECK-NEXT: [[UC_5:%.*]] = icmp ule i32 [[X]], [[Z]]
+; CHECK-NEXT: [[UC_6:%.*]] = icmp ule i32 [[X]], [[A]]
+; CHECK-NEXT: [[RES_9:%.*]] = xor i1 [[UC_5]], [[UC_6]]
+; CHECK-NEXT: [[UC_7:%.*]] = icmp ule i32 [[X]], [[Y]]
+; CHECK-NEXT: [[RES_10:%.*]] = xor i1 [[RES_9]], [[UC_7]]
+; CHECK-NEXT: [[UC_8:%.*]] = icmp ule i32 [[Y]], [[Z]]
+; CHECK-NEXT: [[RES_11:%.*]] = xor i1 [[RES_10]], [[UC_8]]
+; CHECK-NEXT: [[SC_5:%.*]] = icmp sle i32 [[X]], [[Z]]
+; CHECK-NEXT: [[RES_12:%.*]] = xor i1 [[RES_11]], [[SC_5]]
+; CHECK-NEXT: [[SC_6:%.*]] = icmp sle i32 [[X]], [[A]]
+; CHECK-NEXT: [[RES_13:%.*]] = xor i1 [[RES_12]], [[SC_6]]
+; CHECK-NEXT: [[SC_7:%.*]] = icmp sle i32 [[X]], [[Y]]
+; CHECK-NEXT: [[RES_14:%.*]] = xor i1 [[RES_13]], [[SC_7]]
+; CHECK-NEXT: [[SC_8:%.*]] = icmp sle i32 [[Y]], [[Z]]
+; CHECK-NEXT: [[RES_15:%.*]] = xor i1 [[RES_14]], [[SC_8]]
+; CHECK-NEXT: ret i1 [[RES_15]]
+;
+entry:
+ %c.1 = icmp ule i32 %x, %y
+ %c.2 = icmp sle i32 %y, %z
+ %and = and i1 %c.1, %c.2
+ br i1 %and, label %then, label %else
+
+then:
+ %uc.1 = icmp ule i32 %x, %z
+ %uc.2 = icmp ule i32 %x, %y
+ %res.1 = xor i1 %uc.1, %uc.2
+
+ %uc.3 = icmp ule i32 %y, %z
+ %res.2 = xor i1 %res.1, %uc.3
+
+ %uc.4 = icmp ule i32 %x, %a
+ %res.4 = xor i1 %res.2, %uc.4
+
+ %sc.1 = icmp sle i32 %x, %z
+ %res.5 = xor i1 %res.4, %sc.1
+
+ %sc.2 = icmp sle i32 %x, %y
+ %res.6 = xor i1 %res.5, %sc.2
+
+ %sc.3 = icmp sle i32 %y, %z
+ %res.7 = xor i1 %res.6, %sc.3
+
+ %sc.4 = icmp sle i32 %x, %a
+ %res.8 = xor i1 %res.7, %sc.4
+
+ ret i1 %res.8
+
+else:
+ %uc.5 = icmp ule i32 %x, %z
+ %uc.6 = icmp ule i32 %x, %a
+ %res.9 = xor i1 %uc.5, %uc.6
+
+ %uc.7 = icmp ule i32 %x, %y
+ %res.10 = xor i1 %res.9, %uc.7
+
+ %uc.8 = icmp ule i32 %y, %z
+ %res.11 = xor i1 %res.10, %uc.8
+
+ %sc.5 = icmp sle i32 %x, %z
+ %res.12 = xor i1 %res.11, %sc.5
+
+ %sc.6 = icmp sle i32 %x, %a
+ %res.13 = xor i1 %res.12, %sc.6
+
+ %sc.7 = icmp sle i32 %x, %y
+ %res.14 = xor i1 %res.13, %sc.7
+
+ %sc.8 = icmp sle i32 %y, %z
+ %res.15 = xor i1 %res.14, %sc.8
+
+ ret i1 %res.15
+}
diff --git a/llvm/test/Transforms/ConstraintElimination/sge.ll b/llvm/test/Transforms/ConstraintElimination/sge.ll
new file mode 100644
index 000000000000..adb32bf9f5a5
--- /dev/null
+++ b/llvm/test/Transforms/ConstraintElimination/sge.ll
@@ -0,0 +1,252 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -constraint-elimination -S %s | FileCheck %s
+
+declare void @use(i1)
+
+define void @test_1_variable_constraint(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @test_1_variable_constraint(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C_1:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: br i1 [[C_1]], label [[BB1:%.*]], label [[BB2:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[T_1:%.*]] = icmp sge i32 [[X]], [[Y]]
+; CHECK-NEXT: call void @use(i1 [[T_1]])
+; CHECK-NEXT: [[C_2:%.*]] = icmp sge i32 [[X]], 10
+; CHECK-NEXT: call void @use(i1 [[C_2]])
+; CHECK-NEXT: [[C_3:%.*]] = icmp sge i32 [[Y]], [[X]]
+; CHECK-NEXT: call void @use(i1 [[C_3]])
+; CHECK-NEXT: [[C_4:%.*]] = icmp sge i32 10, [[X]]
+; CHECK-NEXT: call void @use(i1 [[C_4]])
+; CHECK-NEXT: ret void
+; CHECK: bb2:
+; CHECK-NEXT: [[T_2:%.*]] = icmp sge i32 [[Y]], [[X]]
+; CHECK-NEXT: call void @use(i1 [[T_2]])
+; CHECK-NEXT: [[F_1:%.*]] = icmp sge i32 [[X]], [[Y]]
+; CHECK-NEXT: call void @use(i1 [[F_1]])
+; CHECK-NEXT: [[C_5:%.*]] = icmp sge i32 [[X]], 10
+; CHECK-NEXT: call void @use(i1 [[C_5]])
+; CHECK-NEXT: [[C_6:%.*]] = icmp sge i32 10, [[X]]
+; CHECK-NEXT: call void @use(i1 [[C_6]])
+; CHECK-NEXT: ret void
+;
+entry:
+ %c.1 = icmp sge i32 %x, %y
+ br i1 %c.1, label %bb1, label %bb2
+
+bb1:
+ %t.1 = icmp sge i32 %x, %y
+ call void @use(i1 %t.1)
+ %c.2 = icmp sge i32 %x, 10
+ call void @use(i1 %c.2)
+ %c.3 = icmp sge i32 %y, %x
+ call void @use(i1 %c.3)
+ %c.4 = icmp sge i32 10, %x
+ call void @use(i1 %c.4)
+ ret void
+
+bb2:
+ %t.2 = icmp sge i32 %y, %x
+ call void @use(i1 %t.2)
+ %f.1 = icmp sge i32 %x, %y
+ call void @use(i1 %f.1)
+ %c.5 = icmp sge i32 %x, 10
+ call void @use(i1 %c.5)
+ %c.6 = icmp sge i32 10, %x
+ call void @use(i1 %c.6)
+ ret void
+}
+
+define void @test_1_constant_constraint(i32 %x) {
+; CHECK-LABEL: @test_1_constant_constraint(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C_1:%.*]] = icmp sge i32 [[X:%.*]], 10
+; CHECK-NEXT: br i1 [[C_1]], label [[BB1:%.*]], label [[BB2:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[T_1:%.*]] = icmp sge i32 [[X]], 10
+; CHECK-NEXT: call void @use(i1 [[T_1]])
+; CHECK-NEXT: [[T_2:%.*]] = icmp sge i32 [[X]], 9
+; CHECK-NEXT: call void @use(i1 [[T_2]])
+; CHECK-NEXT: [[C_2:%.*]] = icmp sge i32 [[X]], 11
+; CHECK-NEXT: call void @use(i1 [[C_2]])
+; CHECK-NEXT: [[C_4:%.*]] = icmp sge i32 10, [[X]]
+; CHECK-NEXT: call void @use(i1 [[C_4]])
+; CHECK-NEXT: ret void
+; CHECK: bb2:
+; CHECK-NEXT: [[T_3:%.*]] = icmp sge i32 11, [[X]]
+; CHECK-NEXT: call void @use(i1 [[T_3]])
+; CHECK-NEXT: [[F_1:%.*]] = icmp sge i32 [[X]], 10
+; CHECK-NEXT: call void @use(i1 [[F_1]])
+; CHECK-NEXT: [[F_1_1:%.*]] = icmp sge i32 [[X]], 10
+; CHECK-NEXT: call void @use(i1 [[F_1_1]])
+; CHECK-NEXT: [[C_5:%.*]] = icmp sge i32 [[X]], 9
+; CHECK-NEXT: call void @use(i1 [[C_5]])
+; CHECK-NEXT: [[C_6:%.*]] = icmp sge i32 1, [[X]]
+; CHECK-NEXT: call void @use(i1 [[C_6]])
+; CHECK-NEXT: ret void
+;
+entry:
+ %c.1 = icmp sge i32 %x, 10
+ br i1 %c.1, label %bb1, label %bb2
+
+bb1:
+ %t.1 = icmp sge i32 %x, 10
+ call void @use(i1 %t.1)
+ %t.2 = icmp sge i32 %x, 9
+ call void @use(i1 %t.2)
+ %c.2 = icmp sge i32 %x, 11
+ call void @use(i1 %c.2)
+ %c.4 = icmp sge i32 10, %x
+ call void @use(i1 %c.4)
+ ret void
+
+bb2:
+ %t.3 = icmp sge i32 11, %x
+ call void @use(i1 %t.3)
+ %f.1 = icmp sge i32 %x, 10
+ call void @use(i1 %f.1)
+
+
+ %f.1.1 = icmp sge i32 %x, 10
+ call void @use(i1 %f.1.1)
+ %c.5 = icmp sge i32 %x, 9
+ call void @use(i1 %c.5)
+ %c.6 = icmp sge i32 1, %x
+ call void @use(i1 %c.6)
+ ret void
+}
+
+define i32 @test1(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C_1:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: br i1 [[C_1]], label [[BB1:%.*]], label [[EXIT:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[C_2:%.*]] = icmp sge i32 [[Y]], [[Z:%.*]]
+; CHECK-NEXT: br i1 [[C_2]], label [[BB2:%.*]], label [[EXIT]]
+; CHECK: bb2:
+; CHECK-NEXT: [[C_3:%.*]] = icmp sge i32 [[X]], [[Z]]
+; CHECK-NEXT: br i1 [[C_3]], label [[BB3:%.*]], label [[EXIT]]
+; CHECK: bb3:
+; CHECK-NEXT: ret i32 10
+; CHECK: exit:
+; CHECK-NEXT: ret i32 20
+;
+entry:
+ %c.1 = icmp sge i32 %x, %y
+ br i1 %c.1, label %bb1, label %exit
+
+bb1:
+ %c.2 = icmp sge i32 %y, %z
+ br i1 %c.2, label %bb2, label %exit
+
+bb2:
+ %c.3 = icmp sge i32 %x, %z
+ br i1 %c.3, label %bb3, label %exit
+
+bb3:
+ ret i32 10
+
+exit:
+ ret i32 20
+}
+
+define i32 @test2(i32 %x, i32 %y, i32 %z, i32 %a) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C_1:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: br i1 [[C_1]], label [[BB1:%.*]], label [[EXIT:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[C_2:%.*]] = icmp sge i32 [[Y]], [[Z:%.*]]
+; CHECK-NEXT: br i1 [[C_2]], label [[BB2:%.*]], label [[EXIT]]
+; CHECK: bb2:
+; CHECK-NEXT: [[C_3:%.*]] = icmp sge i32 [[X]], [[A:%.*]]
+; CHECK-NEXT: br i1 [[C_3]], label [[BB3:%.*]], label [[EXIT]]
+; CHECK: bb3:
+; CHECK-NEXT: ret i32 10
+; CHECK: exit:
+; CHECK-NEXT: ret i32 20
+;
+entry:
+ %c.1 = icmp sge i32 %x, %y
+ br i1 %c.1, label %bb1, label %exit
+
+bb1:
+ %c.2 = icmp sge i32 %y, %z
+ br i1 %c.2, label %bb2, label %exit
+
+bb2:
+ %c.3 = icmp sge i32 %x, %a
+ br i1 %c.3, label %bb3, label %exit
+
+bb3:
+ ret i32 10
+
+exit:
+ ret i32 20
+}
+
+
+define i32 @test3(i32 %x, i32 %y) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C_1:%.*]] = icmp sge i32 [[X:%.*]], 10
+; CHECK-NEXT: br i1 [[C_1]], label [[BB1:%.*]], label [[EXIT:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[C_2:%.*]] = icmp sge i32 [[Y:%.*]], 20
+; CHECK-NEXT: br i1 [[C_2]], label [[BB2:%.*]], label [[EXIT]]
+; CHECK: bb2:
+; CHECK-NEXT: ret i32 10
+; CHECK: exit:
+; CHECK-NEXT: ret i32 20
+;
+entry:
+ %c.1 = icmp sge i32 %x, 10
+ br i1 %c.1, label %bb1, label %exit
+
+bb1:
+ %c.2 = icmp sge i32 %y, 20
+ br i1 %c.2, label %bb2, label %exit
+
+bb2:
+ ret i32 10
+
+exit:
+ ret i32 20
+}
+
+define i32 @test4(i32 %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[C_1:%.*]] = icmp sge i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: br i1 [[C_1]], label [[BB1:%.*]], label [[EXIT:%.*]]
+; CHECK: bb1:
+; CHECK-NEXT: [[C_2:%.*]] = icmp sge i32 [[Y]], [[Z:%.*]]
+; CHECK-NEXT: br i1 [[C_2]], label [[BB2:%.*]], label [[EXIT]]
+; CHECK: bb2:
+; CHECK-NEXT: [[T_1:%.*]] = icmp sge i32 [[X]], [[Z]]
+; CHECK-NEXT: call void @use(i1 [[T_1]])
+; CHECK-NEXT: [[U_1:%.*]] = icmp eq i32 [[X]], [[Z]]
+; CHECK-NEXT: call void @use(i1 [[U_1]])
+; CHECK-NEXT: ret i32 10
+; CHECK: exit:
+; CHECK-NEXT: ret i32 20
+;
+entry:
+ %c.1 = icmp sge i32 %x, %y
+ br i1 %c.1, label %bb1, label %exit
+
+bb1:
+ %c.2 = icmp sge i32 %y, %z
+ br i1 %c.2, label %bb2, label %exit
+
+bb2:
+ %t.1 = icmp sge i32 %x, %z
+ call void @use(i1 %t.1)
+ %u.1 = icmp eq i32 %x, %z
+ call void @use(i1 %u.1)
+ ret i32 10
+
+
+exit:
+ ret i32 20
+}
More information about the llvm-commits
mailing list