[PATCH] D95705: [RISCV] Add initial support for converting fixed vectors to scalable vectors during lowering to use RVV instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:94
+         "Tried to get vector length without V extension support!");
+  assert(RVVVectorBitsMin % 128 == 0 &&
+         "V extension requires vector length in multiples of 128!");
----------------
craig.topper wrote:
> HsiangKai wrote:
> > V has no such requirement or I misunderstood the specification?
> Good point. I blindly copied that from AArch64 and was more focused on getting on to the lowering work.
> 
> What restrictions should we have here?
There are two restrictions in specification. VLEN≥128 and VLEN must be a power of 2.


Repository:
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  https://reviews.llvm.org/D95705/new/

https://reviews.llvm.org/D95705