[PATCH] D95620: [RISCV] Support scalable-vector integer reduction intrinsics

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:436
+      setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
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You list ISD::VECREDUCE_MUL here, but you did not handle ISD::VECREDUCE_MUL in LowerOperation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95620/new/

https://reviews.llvm.org/D95620