[PATCH] D95620: [RISCV] Support scalable-vector integer reduction intrinsics

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck marked an inline comment as done.
frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:915
+    // The lowering for reductions returns a vector whose first element is the
+    // result of the reduction. Use the VMV_X_S node to extract the first
+    // element: that way we can infer information about the sign bits.
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craig.topper wrote:
> Shouldn't we always lower EXTRACT_ELEMENT for types less than XLen to VMV_X_S? Why is knowing sign extension important for this operation, but not any extract element?
Yes, we really should. I'll put up a patch which addresses that first, then can rebase this on top of that.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1681
+  MVT M1VT = MVT::getScalableVectorVT(VecEltVT, NumElts);
+  SDValue Splat0 =
+      DAG.getSplatVector(M1VT, DL, DAG.getConstant(IdentityVal, DL, VecEltVT));
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craig.topper wrote:
> Rename this since its not a Splat of 0 anymore. Also update the commit message.
Done, thanks for reminding me.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95620/new/

https://reviews.llvm.org/D95620