[PATCH] D95659: [RISCV] Initial support of LoopVectorizer for RISC-V Vector.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

In D95659#2530358 <https://reviews.llvm.org/D95659#2530358>, @rogfer01 wrote:

> Hi Kai, are we OK with having a test that goes from IR to assembly in the `Transforms` component?
>
> I'd expect here a vectorized IR test. Then we can add tests those inputs `Codegen` so they generate sensible RVV instructions.

I'd prefer this too.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4576
+      (ElemVT == MVT::f64 && Align == 8))
+    return true;
+
----------------
craig.topper wrote:
> You can probably just the element VTs and then check that Align == ElemVT.getStoreSize() rather than spelling out all of the alignments.
> 
> What is considered misaligned for scalable vectors? Should we be checking the alignement is >= the element size?
Yeah, I agree. For RVV we just need to check that the vectors are at least aligned to the element size, don't we? I reckon `Align >= EltVT.getStoreSize()` is sufficient.


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