[PATCH] D95620: [RISCV] Support scalable-vector integer reduction intrinsics

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck updated this revision to Diff 320091.
frasercrmck added a comment.

- fix identity values for smax,smin,umax,and reductions
- fix RV32 64-bit reductions using 32-bit identity values


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95620/new/

https://reviews.llvm.org/D95620

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll

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