[PATCH] D95620: [RISCV] Support scalable-vector integer reduction intrinsics
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 29 03:13:08 PST 2021
frasercrmck updated this revision to Diff 320091.
frasercrmck added a comment.
- fix identity values for smax,smin,umax,and reductions
- fix RV32 64-bit reductions using 32-bit identity values
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D95620/new/
https://reviews.llvm.org/D95620
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D95620.320091.patch
Type: text/x-patch
Size: 123693 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210129/db632829/attachment-0001.bin>
More information about the llvm-commits
mailing list