[PATCH] D95667: [NFC][RISCV] Remove redundant pseudo instructions for vector load/store.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
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Not all combinations of SEW and LMUL we need to support. For example, we
only need to support [M1 <https://reviews.llvm.org/M1>, M2 <https://reviews.llvm.org/M2>, M4, M8] for SEW = 64. There is no need to
define pseudos for PseudoVLSE64MF8, PseudoVLSE64MF4, and PseudoVLSE64MF2.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95667

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

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