[PATCH] D95489: [AMDGPU] Do not reassign spilled registers

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp:482
+  if (Def && ((Def->isCopy() && Def->getOperand(1).getReg() == PhysReg) ||
+              TII->isSpill(*Def)))
     return false;
----------------
arsenm wrote:
> rampitec wrote:
> > arsenm wrote:
> > > Can you tell if it's a spill from the VirtRegMap instead?
> > I don't see how.
> Does Register::isStackSlot return true here, or does VRM->getStackSlot() != NO_STACK_SLOT tell you?
Both don't:

```
(gdb) p Register::isStackSlot((unsigned)Reg)
$12 = false
(gdb) p VRM->getStackSlot(Reg) == VirtRegMap::NO_STACK_SLOT
$11 = true
```
I.e. it is VRM::isAssignedReg() which is checked in the first place. If not PBQB this shall be considered an RA bug.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95489/new/

https://reviews.llvm.org/D95489