[PATCH] D95489: [AMDGPU] Do not reassign spilled registers

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp:482
+  if (Def && ((Def->isCopy() && Def->getOperand(1).getReg() == PhysReg) ||
+              TII->isSpill(*Def)))
     return false;
----------------
Can you tell if it's a spill from the VirtRegMap instead?


================
Comment at: llvm/test/CodeGen/AMDGPU/nsa-reassign.mir:8-16
+registers:
+  - { id: 0, class: sgpr_256, preferred-register: '$sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7' }
+  - { id: 1, class: sgpr_128, preferred-register: '$sgpr8_sgpr9_sgpr10_sgpr11' }
+  - { id: 2, class: vgpr_32, preferred-register: '$vgpr2' }
+  - { id: 3, class: vgpr_32, preferred-register: '$vgpr4' }
+  - { id: 4, class: vgpr_32, preferred-register: '$vgpr6' }
+  - { id: 5, class: vgpr_32, preferred-register: '$vgpr8' }
----------------
Don't need the registers section, should use the newer :class syntax


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95489/new/

https://reviews.llvm.org/D95489