[PATCH] D95489: [AMDGPU] Do not reassign spilled registers

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

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We cannot call LRM::unassign() if LRM::assign() was never called
before, these are symmetrical calls. There are two ways of
assigning a physical register to virtual, via LRM::assign() and
via VRM::assignVirt2Phys(). LRM::assign() will call the VRM to
assign the register and then update LiveIntervalUnion. Inline
spiller calls VRM directly and thus LiveIntervalUnion never gets
updated. A call to LRM::unassign() then asserts about inconsistent
liveness.

We have to note that not all callers of the InlineSpiller even
have LRM to pass, RegAllocPBQP does not have it, so we cannot
always pass LRM into the spiller.

This patch refuses to reassign a LiveInterval created by a spill
to workaround the problem. In fact we cannot reassign a spill
anyway as all registers of the needed class are occupied and we
are spilling.

Fixes: SWDEV-267996


https://reviews.llvm.org/D95489

Files:
  llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
  llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
  llvm/test/CodeGen/AMDGPU/regbank-reassign.mir

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