[PATCH] D95136: [X86] Fix tile config register spill issue.
Pengfei Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 28 06:28:32 PST 2021
pengfei marked 3 inline comments as done.
pengfei added inline comments.
================
Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:283
+ // But iterating all BBs isn't too expensive here.
+ for (auto I : BBVisitedInfo) {
+ if (I.second.NeedUpdatePred)
----------------
LuoYuanke wrote:
> xiangzhangllvm wrote:
> > The logic here is complex, better to add clear comment to show how we update the Status for BBs.
> WorkList should be clear before this loop?
Not necessary. But adding it seems more robust.
================
Comment at: llvm/lib/Target/X86/X86PreTileConfig.cpp:302
+ // If BB has AMX, its predecessors don't need to be updated again.
+ if (!BBVisitedInfo[*I].HasAMX)
+ BBVisitedInfo[*I].NeedUpdatePred = true;
----------------
LuoYuanke wrote:
> Don't understand this. Can you add a diagram to illustrate it?
Add some comments on line 290.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D95136/new/
https://reviews.llvm.org/D95136
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