[PATCH] D95563: [RISCV] Add initial support for 128-bit fixed vectors with RVV.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D95563#2527569 <https://reviews.llvm.org/D95563#2527569>, @frasercrmck wrote:

> In D95563#2527547 <https://reviews.llvm.org/D95563#2527547>, @craig.topper wrote:
>
>> Maybe. Is it likely that both would be used at the same time? And if they are which one should have priority?
>
> That's what I've been wondering. If it's a possibility we should handle it somewhat gracefully. But I struggle to see us selectively handling certain types with V and others with P, so I reckon we'd just make a top-level all-or-nothing choice, possibly based on a user option. I guess I intuitively think P takes priority since it's specialised for those types?
>
> This isn't something I've solved for myself, but it was making me hesitant to update my fixed-length patches.

At least in the td file patterns we shouldn’t have a problem with types overlapping if we use 128 bit for fixed vectors with V. I think we may eventually end up needing to lower fixed vectors to a user controlled vector width. Which likely means we’ll eventually need to lower fixed vectors to scalable vectors with a VL argument earlier than isel patterns. I think AArch64 has some support for something similar.


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