[PATCH] D95568: [RISCV] Add support for scalable vector fneg using vfsgnjn.vv

Thu Jan 28 01:37:55 PST 2021

frasercrmck added inline comments.

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Comment at: llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode-rv32.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
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craig.topper wrote:
> frasercrmck wrote:
> > Can we also test RV64 as part of this test?
> You mean ,ergo the two files?
Oh, I think I got mixed up between this and the fixed-length patch! I thought there wasn't a separate RV64 test. I'd be happy to merge them since I think the IR is identical, but I'll leave that up to you.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95568/new/

https://reviews.llvm.org/D95568