[PATCH] D95568: [RISCV] Add support for scalable vector fneg using vfsgnjn.vv
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 28 01:34:19 PST 2021
craig.topper added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode-rv32.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
----------------
frasercrmck wrote:
> Can we also test RV64 as part of this test?
You mean ,ergo the two files?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D95568/new/
https://reviews.llvm.org/D95568
More information about the llvm-commits
mailing list