[PATCH] D95292: [AArch64] Add vector saturating add intrinsic costs

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:249
+    unsigned Instrs =
+        LT.second.getScalarSizeInBits() == RetTy->getScalarSizeInBits() ? 1 : 4;
+    if (any_of(ValidSatTys, [&LT](MVT M) { return M == LT.second; }))
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fhahn wrote:
> are there test cases for that? 
For the Instrs == 4 case? Yeah, those are cases like:
; RECIP-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> undef, <2 x i16> undef)


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Comment at: llvm/test/Analysis/CostModel/AArch64/arith-ssat.ll:79
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V32I8 = call <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8> undef, <32 x i8> undef)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef)
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret i32 undef
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fhahn wrote:
> perhaps throw in an odd number of vector elements as well?
Will do.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95292/new/

https://reviews.llvm.org/D95292