[PATCH] D95491: [RISCV] Group the legal vector types into lists we can iterator over in the RISCVISelLowering constructor

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Remove the RISCVVMVTs namespace because I don't think it provides
a lot of value. If we change the mappings we'd likely have to add
or remove things from the list anyway.

Add a wrapper around addRegisterClass that can determine the
register class from the fixed size of the type.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D95491

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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