[PATCH] D95432: AMDGPU/GlobalISel: Combine uniform icmp with select
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 26 06:31:54 PST 2021
arsenm added a comment.
This should also apply to conditional branches, but the user doesn't actually matter. This is really a generic combine for (trunc (bool_ext_type bool_producer))
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Comment at: llvm/lib/Target/AMDGPU/AMDGPUCombine.td:44
+ (defs root:$select, uniform_icmp_select_matchdata:$matchinfo),
+ (match (wip_match_opcode G_SELECT):$select,
+ [{ return RegBankHelper.matchUniformICmpSelect(*${select}, ${matchinfo}); }]),
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The select part here isn't essential, but the matcher here wants a specific opcode. I guess you could bypass the generated combine matcher and just call this combine in a switch, or at least add the relevant G_BRCOND user
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Comment at: llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp:90
+ ICMP.getOperand(0), ICMP.getOperand(2), ICMP.getOperand(3));
+ MI.getOperand(1).setReg(MatchInfo.ICmpReg);
+ ICMP.eraseFromParent();
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Changing the instruction without notifying the observer
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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/combine-uniform-icmp-select.mir:37-62
+ ; CHECK: S_ENDPGM 0
+ %4:sgpr(s32) = COPY $sgpr0
+ %5:sgpr(s32) = COPY $sgpr1
+ %6:sgpr(s32) = COPY $sgpr2
+ %7:sgpr(s32) = COPY $sgpr3
+ %8:sgpr(s32) = COPY $sgpr4
+ %9:sgpr(s32) = COPY $sgpr5
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Most of these instructions aren't relevant to the combine. You can also directly emit copies from 64-bit SGPRs even though we emit them normally as separate 32-bit copies
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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/combine-uniform-icmp-select.mir:116-142
+ %9:sgpr(s32) = COPY $sgpr3
+ %10:sgpr(s32) = COPY $sgpr4
+ %11:sgpr(s32) = COPY $sgpr5
+ %12:sgpr(s32) = COPY $sgpr6
+ %13:sgpr(s32) = COPY $sgpr7
+ %14:vgpr(s32) = COPY $vgpr0
+ %15:vgpr(s32) = COPY $vgpr1
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Ditto
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https://reviews.llvm.org/D95432/new/
https://reviews.llvm.org/D95432
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