[PATCH] D95025: [RISCV] Add a test showing incorrect codegen

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

In D95025#2521522 <https://reviews.llvm.org/D95025#2521522>, @luismarques wrote:

> In D95025#2521433 <https://reviews.llvm.org/D95025#2521433>, @jrtc27 wrote:
>
>> I suspect it wasn't used because this is an IR->MIR test; there's utils/update_mir_test_checks.py for that (works with both IR and MIR input).
>
> I tried to use that tool for `llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir`, to see if it would be practical for the growing list of RVV tests (less than 40% of them currently use it), but it crashes with:
> `KeyError: 'vadd_vint64m1'`.

That's because there's a test to print assembly. MIR input tests are intended for unit-testing passes or sets of passes; if you want to be looking at the final assembly, that should be an IR test, but the MIR after finalize-isel should be more than sufficient in almost all cases.


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  https://reviews.llvm.org/D95025/new/

https://reviews.llvm.org/D95025