[PATCH] D95234: [RISCV] Define different pseudo instructions for different FPR.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:42
 
+// We only model FPR32 for V instructions in RISCVInstrInfoV.td.
+// FP16/FP32/FP64 registers are alias each other. Convert FPR16 and FPR64
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frasercrmck wrote:
> craig.topper wrote:
> > Please mark this with a FIXME to cleanup. Fraser or I can take care of it as a follow up.
> Yeah, no problem, I can take a look.
@frasercrmck I'm looking at this and might be proposing changes to this patch as well.


Repository:
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  https://reviews.llvm.org/D95234/new/

https://reviews.llvm.org/D95234