[PATCH] D95289: [TargetLowering][RISCV] Don't turn (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper

[Luís Marques via Phabricator via llvm-commits]

luismarques accepted this revision.
luismarques added a subscriber: mundaym.
luismarques added a comment.
This revision is now accepted and ready to land.

Makes sense to me.

@craig.topper are you using the correct clang-format config? Remember to fix the minor formatting issue.



================
Comment at: llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll:22
 ; RV32IFD-NEXT:    fsd ft0, 8(sp) # 8-byte Folded Spill
-; RV32IFD-NEXT:    call func
+; RV32IFD-NEXT:    call func at plt
 ; RV32IFD-NEXT:    sw a0, 16(sp)
----------------
jrtc27 wrote:
> frasercrmck wrote:
> > I'm not familiar with this syntax: is this just a result of running the `update_llc_test_checks.py` script, and given that `call func` matches `call func at plt` it was passing anyway?
> Yes, these check lines just predate full PIC support
What confuses me about this is that @mundaym had fairly recently regenerated all of the tests, which added spill comments and `@plt` stuff. Why didn't `update_llc_test_checks.py` add the `@plt` here then?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95289/new/

https://reviews.llvm.org/D95289