[PATCH] D95289: [TargetLowering][RISCV] Don't turn (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll:22
 ; RV32IFD-NEXT:    fsd ft0, 8(sp) # 8-byte Folded Spill
-; RV32IFD-NEXT:    call func
+; RV32IFD-NEXT:    call func at plt
 ; RV32IFD-NEXT:    sw a0, 16(sp)
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frasercrmck wrote:
> I'm not familiar with this syntax: is this just a result of running the `update_llc_test_checks.py` script, and given that `call func` matches `call func at plt` it was passing anyway?
Yes, these check lines just predate full PIC support


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  https://reviews.llvm.org/D95289/new/

https://reviews.llvm.org/D95289