[PATCH] D94465: [RISCV] Frame handling for RISC-V V extension. (2nd. version)

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:198
+        .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
+    if (!((RISCVVPseudosTable::getPseudoInfo(MI.getOpcode()) != nullptr) &&
+          MI.mayLoadOrStore()))
----------------
rogfer01 wrote:
> I'm not sure whether we won't get some cases where the frame index is fixed but the instruction is actually a RVV load/store.
> 
> Something from IR like below (assume the size of the array is correct for the runtime `vscale` value)
> 
> ```lang=llvm
> %array = alloca [64 x double]
> %vptr = bitcast [64 x double]* %array to <vscale x 1 x double>*
> %v = load <vscale x 1 x double>, <vscale x 1 x double>* %vptr
> ```
We may need to add an option to tell the compiler what vector length we are compiling for. Otherwise, how do we confirm the VLS length equals to RVV vector length? Another question is which LMUL do we support to do VLS load/store through RVV instructions, LMUL = 1 only?

I will leave a FIXME here.


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https://reviews.llvm.org/D94465