[PATCH] D95169: [RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGd65e8ee507f8: [RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95169/new/

https://reviews.llvm.org/D95169

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll


Index: llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
===================================================================
--- llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -27,8 +27,7 @@
 ;
 ; RV32IBT-LABEL: cmovcc64:
 ; RV32IBT:       # %bb.0: # %entry
-; RV32IBT-NEXT:    addi a5, zero, 123
-; RV32IBT-NEXT:    xor a5, a0, a5
+; RV32IBT-NEXT:    addi a5, a0, -123
 ; RV32IBT-NEXT:    cmov a0, a5, a3, a1
 ; RV32IBT-NEXT:    cmov a1, a5, a4, a2
 ; RV32IBT-NEXT:    ret
@@ -45,8 +44,7 @@
 ;
 ; RV64IBT-LABEL: cmovcc64:
 ; RV64IBT:       # %bb.0: # %entry
-; RV64IBT-NEXT:    addi a3, zero, 123
-; RV64IBT-NEXT:    xor a0, a0, a3
+; RV64IBT-NEXT:    addi a0, a0, -123
 ; RV64IBT-NEXT:    cmov a0, a0, a2, a1
 ; RV64IBT-NEXT:    ret
 entry:
@@ -133,8 +131,7 @@
 ;
 ; RV64IBT-LABEL: cmovcc128:
 ; RV64IBT:       # %bb.0: # %entry
-; RV64IBT-NEXT:    addi a5, zero, 123
-; RV64IBT-NEXT:    xor a5, a0, a5
+; RV64IBT-NEXT:    addi a5, a0, -123
 ; RV64IBT-NEXT:    cmov a0, a5, a3, a1
 ; RV64IBT-NEXT:    cmov a1, a5, a4, a2
 ; RV64IBT-NEXT:    ret
@@ -434,8 +431,7 @@
 ;
 ; RV32IBT-LABEL: cmovccdep:
 ; RV32IBT:       # %bb.0: # %entry
-; RV32IBT-NEXT:    addi a4, zero, 123
-; RV32IBT-NEXT:    xor a0, a0, a4
+; RV32IBT-NEXT:    addi a0, a0, -123
 ; RV32IBT-NEXT:    cmov a1, a0, a2, a1
 ; RV32IBT-NEXT:    cmov a0, a0, a3, a1
 ; RV32IBT-NEXT:    add a0, a1, a0
@@ -462,8 +458,7 @@
 ;
 ; RV64IBT-LABEL: cmovccdep:
 ; RV64IBT:       # %bb.0: # %entry
-; RV64IBT-NEXT:    addi a4, zero, 123
-; RV64IBT-NEXT:    xor a0, a0, a4
+; RV64IBT-NEXT:    addi a0, a0, -123
 ; RV64IBT-NEXT:    cmov a1, a0, a2, a1
 ; RV64IBT-NEXT:    cmov a0, a0, a3, a1
 ; RV64IBT-NEXT:    addw a0, a1, a0
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -778,10 +778,15 @@
 let Predicates = [HasStdExtZbt] in {
 def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)),
           (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+
 def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3),
           (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3),
+          (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1),
+          (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs3),
           (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),


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