[PATCH] D95234: [RISCV] Define different pseudo instructions for different FPR.

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

L:GTM with that one comment.



================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:42
 
+// We only model FPR32 for V instructions in RISCVInstrInfoV.td.
+// FP16/FP32/FP64 registers are alias each other. Convert FPR16 and FPR64
----------------
Please mark this with a FIXME to cleanup. Fraser or I can take care of it as a follow up.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95234/new/

https://reviews.llvm.org/D95234