[PATCH] D95214: [RISCV]A bug when llc -O0 vfmv.f.s.ll

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

In D95234 <https://reviews.llvm.org/D95234>, I defined different pseudo instructions for different floating-point register classes. The floating-point vector pseudo instructions have correct register class information in D95234 <https://reviews.llvm.org/D95234>. I think it also solves the bug you encountered.


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95214/new/

https://reviews.llvm.org/D95214