[PATCH] D95016: [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added inline comments.


================
Comment at: clang/include/clang/Basic/riscv_vector.td:157
+  // Reads or writes "memory" or has other side-effects.
+  bit HasSideEffects = 0;
+
----------------
 Where will it be used？Will just marking sideeffect in the llvm/include/llvm/IR/IntrinsicsRISCV.td file not meet the requirement? Thanks.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D95016/new/

https://reviews.llvm.org/D95016