[PATCH] D94903: [RISCV] Implement vlxseg intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vlxseg-rv32.ll:12
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vlxseg3ei16.v v15, (a0), v16
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v15_v16_v17
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This violates "For vector indexed segment loads, the destination vector register groups cannot overlap the source vector register group (specified by vs2), else an illegal instruction exception is raised." right?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94903/new/

https://reviews.llvm.org/D94903