[PATCH] D94931: [RISCV] Add attribute support for all supported extensions

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/attributes.ll:49
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
+; RV32B: .attribute 5, "rv32i2p0_b0p92_zbb0p92_zbc0p92_zbe0p92_zbf0p92_zbm0p92_zbp0p92_zbr0p92_zbs0p92_zbt0p92"
+; RV32V: .attribute 5, "rv32i2p0_v0p9"
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I suppose given the way this works in LLVM it would add even more duplication to reverse the logic for enabling sub-extensions and specify only `rv32i2p0_b0p92`, but @kito-cheng, can you please confirm what GCC does in a case like this?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94931/new/

https://reviews.llvm.org/D94931