[PATCH] D94286: [RISCV] Add a VL output to vleff intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 318090.
craig.topper added a comment.

-Add tests for unused results on the masked intrinsic
-Make the masked intrinsic have "side effects"
-Use the default read/write memory property instead of IntrReadMem+IntrHasSideEffects which doesn't work correctly without tablegen changes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94286/new/

https://reviews.llvm.org/D94286

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
  llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll

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