[PATCH] D94286: [RISCV] Add a VL output to vleff intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:130
+                     LLVMMatchType<1>],
+                    [NoCapture<ArgIndex<1>>, IntrReadMem]>, RISCVVIntrinsic;
   // For strided load
----------------
This should have IntrHasSideEffects


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94286/new/

https://reviews.llvm.org/D94286