[PATCH] D56387: [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE

Roman Lebedev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 20 06:52:23 PST 2021


lebedev.ri added a comment.

Seems fine to me, thanks.



================
Comment at: llvm/test/CodeGen/X86/vector-trunc.ll:392-403
+; SSE2-NEXT:    psrad $16, %xmm1
+; SSE2-NEXT:    psrad $16, %xmm0
+; SSE2-NEXT:    packssdw %xmm1, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSSE3-LABEL: trunc8i32_8i16_ashr:
+; SSSE3:       # %bb.0: # %entry
----------------
lebedev.ri wrote:
> I'm not very sure it's an improvement
Looks like for pre-SSE41 we still fail to detect high bits as zeros?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56387/new/

https://reviews.llvm.org/D56387



More information about the llvm-commits mailing list