[PATCH] D94590: [RISCV] Add ISel patterns for scalable mask exts & truncs

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM with that one comment.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1229
+  // Only custom-lower extensions from mask types
+  if (!VecVT.isVector() || !Src.getValueType().isVector() ||
+      Src.getValueType().getVectorElementType() != MVT::i1)
----------------
Why do we need to check that both VecVT and Src.getValueType() are vectors? Don't they always match?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94590/new/

https://reviews.llvm.org/D94590