[PATCH] D94589: [RISCV] Add intrinsics for vector AMO instructions

[ShihPo Hung via Phabricator via llvm-commits]

arcbbb marked 2 inline comments as done.
arcbbb added inline comments.


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Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:476
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty, llvm_anyvector_ty,
+                     llvm_anyint_ty],
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craig.topper wrote:
> Is the value the same type as the result? Can we use LLVMMatchType<0> for it?
yes, thanks!


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:107
+}
+
 // Output pattern for X0 used to represent VLMAX in the pseudo instructions.
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khchen wrote:
> vlxe and vlse have the same logic and I think they can reuse above utility functions, right?
> Do you have a plan to update them (vlxe and vlse) and make the same logic with consistent implementation?  maybe it could be in another patch.
sure!


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D94589