[PATCH] D94796: [RISCV] Add scalable vector truncate patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:88
   SPLAT_VECTOR_I64,
+  // Truncates a RVV integer vector by one power-of-two.
+  TRUNCATE_VECTOR,
----------------
craig.topper wrote:
> Worth just making this VNSRL? Will we end up with a DAG combine to combine shifts+truncate?
> Worth just making this VNSRL? Will we end up with a DAG combine to combine shifts+truncate?




================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:88
   SPLAT_VECTOR_I64,
+  // Truncates a RVV integer vector by one power-of-two.
+  TRUNCATE_VECTOR,
----------------
craig.topper wrote:
> craig.topper wrote:
> > Worth just making this VNSRL? Will we end up with a DAG combine to combine shifts+truncate?
> > Worth just making this VNSRL? Will we end up with a DAG combine to combine shifts+truncate?
> 
> 
Though I guess then you have to use splat vector and deal with type legalization there. So maybe its not worth that complexity yet.


Repository:
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  https://reviews.llvm.org/D94796/new/

https://reviews.llvm.org/D94796