[PATCH] D94796: [RISCV] Add scalable vector truncate patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:88
   SPLAT_VECTOR_I64,
+  // Truncates a RVV integer vector by one power-of-two.
+  TRUNCATE_VECTOR,
----------------
Worth just making this VNSRL? Will we end up with a DAG combine to combine shifts+truncate?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94796/new/

https://reviews.llvm.org/D94796