[PATCH] D94590: [RISCV] Add ISel patterns for scalable mask exts & truncs

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:374
+      // Custom-lower extensions and truncations to/from mask types
+      setOperationAction(ISD::ANY_EXTEND, VT, Custom);
+      setOperationAction(ISD::SIGN_EXTEND, VT, Custom);
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Technically this should only be for the legal types. But I guess we don't expect to see scalable vectors that need to be type legalized?


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1178
+
+  // FIXME: Be careful about splatting constants, as getConstant can't
+  // legalize vXi64 on RV32
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I don't think we should be creating scalars with MVT::i64 type on RV32 here. It will usually work because a round of type legalization is called after vector op legalization. Which will legalize the ISD::SPLAT_VECTOR. But if for some reason a mask extension is ever introduced during LegalizeDAG, the scalar type wouldn't get legalized. Can we just detect this case and emit SPLAT_VECTOR_I64 here?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94590/new/

https://reviews.llvm.org/D94590