[PATCH] D94590: [RISCV] Add ISel patterns for scalable mask exts & truncs

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck marked an inline comment as done.
frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:516
+                zero_splat, 1, (vti.Mask $rs1), VLMax, vti.SEW)>;
+  def : Pat<(vti.Mask (trunc (vti.Vector vti.RegClass:$rs1))),
+            (!cast<Instruction>("PseudoVMSNE_VI_"#vti.LMul.MX)
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craig.topper wrote:
> trunc would probably be better custom lowered. We should be able to remove the AND if the input has enough 0 bits. Not sure if SimplifyDemandedBits is capable of that for scalable vectors yet.
> 
> sext/zext/anyext might also be better custom lowered just to cut down on patterns. Our isel table is approaching 1MB. The next largest target is at about 600K.
Yeah, fair enough. These are good candidates for that since they're just re-expressed as standard nodes. I've done both in custom lowering functions.


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