[PATCH] D94504: [SVE] Add ISel pattern for addvl

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes updated this revision to Diff 316155.
c-rhodes edited the summary of this revision.
c-rhodes added a comment.

Rebased. Committed update_llc_test_checks.py changes separately to reduce the diff (thanks for suggestion @sdesmalen).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94504/new/

https://reviews.llvm.org/D94504

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/split-vector-insert.ll
  llvm/test/CodeGen/AArch64/sve-gep.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
  llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
  llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
  llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
  llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll

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