[PATCH] D94504: [SVE] Add ISel pattern for addvl
Cullen Rhodes via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 12 08:57:09 PST 2021
c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, david-arm, cameron.mcinally.
Herald added subscribers: NickHung, psnobl, hiraditya, tschuett.
Herald added a reviewer: efriedma.
c-rhodes requested review of this revision.
Herald added a project: LLVM.
A couple of tests were re-generated with update_llc_test_checks.py so it may
appear to be a lot of changes but most there are NFC.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D94504
Files:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/split-vector-insert.ll
llvm/test/CodeGen/AArch64/sve-gep.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
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