[PATCH] D90853: [RISCV] Add DAG nodes to represent read/write CSR

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

Hi Serge,

> Using `X0` as output is just a trick to have a new instruction without spending opcode. Actually such instruction does not define `X0`. What is the benefit of exposing this low-level encoding feature in high-level structures?

My suggestion was to avoid the situation where we have two machine instructions that overlap in their semantics. This entails that a later pass that analyses CSRs should take into account those write only forms in addition to the actual instructions. However, maybe this is not a practical issue. The number of CSR instructions is not large. It may also happen that SelectionDAG will never select a CSR write instruction that writes to `X0`. Or if it does, we would always use the new write-only form that you suggest.

I'm not sure if we would want to prefix those write-only versions with `Pseudo`? (like it happens with other instructions that exist for the purpose of Codegen).


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https://reviews.llvm.org/D90853