[PATCH] D93804: [RISCV] Spilling for RISC-V V extension.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:97
+  // enabled. See llvm/test/CodeGen/RISCV/rvv/spill-vector-csr.ll.
+  if (TFI->hasFP(MF) || Subtarget.hasStdExtV())
     markSuperRegs(Reserved, RISCV::X8); // fp
----------------
craig.topper wrote:
> frasercrmck wrote:
> > HsiangKai wrote:
> > > frasercrmck wrote:
> > > > Should `hasFP` not pessimistically return true if V is enabled?
> > > Do you mean to move Subtarget.hasStdExtV() into hasFP()? To consider spilling, it seems reasonable.
> > Yeah, that's what I meant. I believe I had a thought a few hours after that comment why you might not want `hasStdExtV` in `hasFP`, but I've forgotten it now.
> I don't see an equivalent of this in AArch64 when SVE is enabled. How are the avoiding needing a frame pointer?
Indeed, it is possible to access frame objects without reserving frame pointer when there is any RVV objects on the stack. If we do not leverage frame pointer when there is any RVV objects, all frame object accesses will need do some polynomial calculation.

Now, there is a new type to represent two dimensions stack offset. I could try to implement it without reserving the frame pointer.


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  https://reviews.llvm.org/D93804/new/

https://reviews.llvm.org/D93804