[PATCH] D93804: [RISCV] Spilling for RISC-V V extension.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:851
     if (*Size)
-      CommentOS << *Size << "-byte Folded Reload\n";
+      (*Size == static_cast<unsigned>(MemoryLocation::UnknownSize)) ?
+        CommentOS << "Unknown size Folded Reload\n" :
----------------
Use if/else here. The conditional operator with no assignment looks kind of strange.


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Comment at: llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp:858
     if (*Size)
-      CommentOS << *Size << "-byte Folded Spill\n";
+      (*Size == static_cast<unsigned>(MemoryLocation::UnknownSize)) ?
+        CommentOS << "Unknown size Folded Spill\n" :
----------------
Same here


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:97
+  // enabled. See llvm/test/CodeGen/RISCV/rvv/spill-vector-csr.ll.
+  if (TFI->hasFP(MF) || Subtarget.hasStdExtV())
     markSuperRegs(Reserved, RISCV::X8); // fp
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frasercrmck wrote:
> HsiangKai wrote:
> > frasercrmck wrote:
> > > Should `hasFP` not pessimistically return true if V is enabled?
> > Do you mean to move Subtarget.hasStdExtV() into hasFP()? To consider spilling, it seems reasonable.
> Yeah, that's what I meant. I believe I had a thought a few hours after that comment why you might not want `hasStdExtV` in `hasFP`, but I've forgotten it now.
I don't see an equivalent of this in AArch64 when SVE is enabled. How are the avoiding needing a frame pointer?


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  https://reviews.llvm.org/D93804/new/

https://reviews.llvm.org/D93804