[PATCH] D94344: [CodeGen] Try to make the print of memory operand alignment a little more user friendly.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 315544.
craig.topper added a comment.

Modify existing memory alignment test in memory_operands.mir to test more combinations of align/basealign presence.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94344/new/

https://reviews.llvm.org/D94344

Files:
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.h
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
  llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
  llvm/test/CodeGen/MIR/X86/memory-operands.mir
  llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/load.mir
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s32.mir
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/long_ambiguous_chain_s64.mir
  llvm/test/CodeGen/Mips/GlobalISel/regbankselect/store.mir
  llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
  llvm/test/CodeGen/X86/avoid-sfb-offset.mir
  llvm/test/CodeGen/X86/bug47278.mir

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