[PATCH] D94286: [RISCV] Add a VL output to vleff intrinsics.

[Craig Topper via Phabricator via llvm-commits]

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The fault-only-first-load instructions can reduce VL if an element
other than element 0 triggers a memory fault. This can be used to
vectorize loops with data dependent exit conditions like strcmp or
strlen.

This patch adds a VL output to these intrinsics so that the new
VL value can be captured by software. This will be expanded to
'csrr gpr, vl' after the vleff instruction during SelectionDAG.

By doing this with one intrinsic we are able to guarantee that the
csrr reads the VL value produced by the vleff instruction. Having
it as a separate intrinsic would make it impossible to guarantee
ordering without making every other vector intrinsic have side
effects.

The intrinsics are expanded during lowering into two ISD nodes
that are glued and chained together. These ISD nodes will go
through isel separately, but should maintain the glue so that they
get emitted adjacent by InstrEmitter.

I'm not sure we really need the chain through the READ_VL node.
Having the chain prevents it from being removed if it isn't used.
That might be too conservative in some case, but most likely
you'll need to use the vl to adjust a pointer. I'm also not sure
we need HasSideEffects on these instructions, the register dependency
might be enough, but I'd like to play it safe for now.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94286

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/CodeGen/Analysis.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll

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