[PATCH] D94249: [RISCV] Custom lower ISD::VSCALE.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: HsiangKai, evandro, frasercrmck, rogfer01.
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This patch custom lowers ISD::VSCALE into a rdcsr vlenb followed
by a shift right by 3 followed by a multiply by the scale amount.

I've added computeKnownBits support to indicate that the csrr vlenb
always produces 3 trailng bits of 0s so the shift right is "exact".
This allows the shift and multiply sequence to be nicely optimized
into a single shift or removed completely when the scale amount is
a power of 2.

The non power of 2 case multiplying by 24 is still producing
suboptimal code. We could remove the right shift and use a
multiply by 3. Hopefully we can improve DAG combine to fix that
since it's not unique to this sequence.

This replaces D94144 <https://reviews.llvm.org/D94144>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94249

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll

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