[PATCH] D94168: [RISCV] Add scalable vector icmp ISel patterns

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:232
+// 12.8. Vector Integer Comparison Instructions
+defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ,  "PseudoVMSEQ">;
+defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE,  "PseudoVMSNE">;
----------------
craig.topper wrote:
> What is the splat for VX/VI is on the LHS?
Ah, good spot. I had assumed constants were canonicalized to the RHS like they are with scalar/fixed-length vectors.

I've now updated `llvm::isConstOrConstSplat` to handle `SPLAT_VECTOR` and it "just works". I also see further optimization such as for `uge v, 0`:

```
-; CHECK-NEXT:    vmv.v.i v25, 0
-; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    vmset.m v0
```

That doesn't solve the problem for VX though. I'd probably suggest a custom combine for that, to avoid too much pattern complication. Any thoughts about that?


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https://reviews.llvm.org/D94168