[PATCH] D94163: [RISCV] Set dependency on floating point CSRs, 1/3

[Serge Pavlov via Phabricator via llvm-commits]

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There are dependencies between floating point instructions that were
missed from the target description. They involve special registers that
keep exception flags and rounding mode. Most FP instructions can set
accrued exception flags, so they are implicit definitions for 'fflags'.
Instructions that use dynamic rounding mode depend on the content of
'frm', they represent implicit uses of this register. These dependencies
impose restrictions on the ordering of FP instructions and must be
provided to the compiler.

This set of patches defines three variants for each instruction that can
be dependent on rounding mode:

- variant for static rounding mode. Only defines 'fflags'.
- variant for dynamic rounding mode. Defines 'fflags', depends on 'frm'.
- variant for default FP environment. Has no implicit defs or uses.

The variant for default FP environment is defined as if it does not
change any register implicitly, although the real instruction changes
'fflags'. It should not be an issue, as in the default mode the
exception flags are ignored (see: https://llvm.org/docs/LangRef.html#floatenv).
Ignoring changes of 'fflags' prevents from appearing output dependencies.

The change is split into several parts to facilitate review. This part
implements the dependency for instructions with three input registers.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D94163

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/double-arith.ll
  llvm/test/CodeGen/RISCV/float-arith.ll
  llvm/test/CodeGen/RISCV/half-arith.ll

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