[PATCH] D94073: [RISCV] Add vector integer mul/mulh/div/rem ISel patterns

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

In D94073#2480355 <https://reviews.llvm.org/D94073#2480355>, @craig.topper wrote:

> I think this specific issue on REM should be fixed after 4ef91f5871a3c38bb2324f89b47a2a845e8a33fd <https://reviews.llvm.org/rG4ef91f5871a3c38bb2324f89b47a2a845e8a33fd>

Thanks, Craig. I mulled over doing that same thing. Hopefully it buys us enough time to fix the issue properly.

Yeah, I thought custom-lowering was a push. I can also see how easy it'd be to get stuck in a loop if you called any other methods when creating this constant. I was thinking you could maybe support this with bitcasts and shifts but it'd be expensive. I might bring this up in the SVE call and see if anyone has ideas.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94073/new/

https://reviews.llvm.org/D94073