[PATCH] D94073: [RISCV] Add vector integer mul/mulh/div/rem ISel patterns

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck updated this revision to Diff 314816.
frasercrmck added a comment.

- rebase and reenable urem tests


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94073/new/

https://reviews.llvm.org/D94073

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll

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