[PATCH] D94144: [RISCV] Support vscale intrinsic and ISDNode.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2330
 
+def : Pat<(int_vscale), (read_vscale)>;
+def : Pat<(vscale 0), (i64 X0)>;
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I think int_vscale becomes (vscale 1) in SelectionDAGBuilder so we can probably drop this pattern?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D94144/new/

https://reviews.llvm.org/D94144